1. Field of the Invention
The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus such as a dot image type laser printer, comprising an image data synchronizing circuit for transferring image data to a printer engine in synchronous with image data sent from a host computer.
2. Description of the Prior Art
In a conventional dot image type printer such as a laser printer, a printer controller receives image information data such as character codes sent from a host computer, develops them into dot image data on a bit map memory, and stores the developed dot image data therein. For example, after dot image data of one page are stored therein, they are transferred to a printer engine to print an image of dot image data on a printing paper.
Up to now, accompanying with lowering of the cost of the laser printers of this type, it has been requested that the manufacturing cost of a printer controller provided therein is lowered.
In a conventional printer controller, there is provided a hardware circuit for imaging dot images on a bit map memory. In a conventional hardware circuit for the printer controller, there is used an expensive LSI for controlling image data and also is used an additional peripheral circuit.
Further, in a conventional LSI for processing image data, there is provided a line buffer memory of a dynamic random access memory (referred as to a DRAM hereinafter) which performs a refresh operation even while white image data are outputted to a printer engine.
Furthermore, without any line buffer memory, there is provided a logic circuit of hardware for synchronizing image data utilizing a DMA transfer method, which are not transferred through a CPU.
For example, if a CPU for controlling a printer controller controls a process for transferring image data to a printer engine in synchronous with image data sent from a host computer, it is supposed that a circuit of hardware can be miniaturized. However, a load applied to the CPU with respect to the above process for transferring image data becomes relatively large, and then, the throughput of the CPU is lowered, and the CPU can not perform the other processes. Therefore, if this problem is not solved, the CPU can not be made to control the above process for transferring image data.
In a conventional dot image type laser printer having a printing speed of six sheets per minute and a resolution of 300 dpi, a frequency of an image data synchronizing clock signal is in the range from about 1.5 MHz to about 2 MHz, and namely, the period thereof is in the range from about 660 nsec. to about 500 nsec.. In the above-mentioned conventional laser printer, it is difficult for a CPU to output image data to a printer engine in this speed. Therefore, it is necessary to provide an image data synchronizing circuit for synchronizing image data sent from a host computer with them to be outputted to the printer engine so that the CPU operates in a frequency of the image data clock signal which is lower than that of conventional one.
In the case that a CPU writes image data of eight bits in parallel form in a parallel to serial converter and the converted serial image data are outputted to a printer engine, a write request signal WRREQ for representing a write timing of the CPU becomes a signal having a period of about 4.0 .mu.sec. to 5.3 .mu.sec., which a general CPU can handle, practically. However, it is necessary to perform the write operation of image data for a time interval of one synchronizing clock signal VCLK after the above-mentioned write request signal WRREQ is generated. It is difficult to detect the write request signal WRREQ by software, and also to output image data sent from a host computer to a printer engine in synchronous with them. Therefore, it is necessary to provide a method for processing image data without software.
For example, if there is provided a logic circuit only for reading out image data stored in a bit map memory, a hardware circuit thereof becomes complicated since a CPU and the logic circuit access the bit map memory.
Further, if there is used a method for utilizing a ready signal provided in a CPU, the above-mentioned write request signal WRREQ is used as it is as the ready signal for the CPU. Upon writing image data in a parallel to serial converter, when the write request signal WRREQ is a low level, a wait state is inserted into the CPU, and then, image data processed by the CPU can be synchronized with image data to be outputted to a printer engine. Thus, image data are outputted from the CPU to the printer engine, however, upon outputting image data to the printer engine or upon printing image data of one page, the CPU can not perform the other processes. Therefore, it is a possibility of stopping a communication with the host computer upon printing image data, and also there is a possibility that the CPU can not perform an urgent error process.
If a line buffer memory of a DRAM is used, a printer controller can be easily miniaturized since the DRAM is highly integrated. However, generally, it is necessary to provide a refresh circuit for refreshing a DRAM. Further, it is necessary to generate a refresh timing signal so that the DRAM is refreshed when both the reading operation and the writing operation are not performed. Therefore, even though there is used a line buffer memory of a DRAM, the printer controller can not be always miniaturized.